Description
1. General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring
individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q
outputs. The reset is an asynchronous active LOW input and operates independently of
the clock input. The J and K inputs control the state changes of the flip-flops as described
in the mode select function table. The J and K inputs must be stable one set-up time prior
to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp
diodes that enable the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
The 74HC107: CMOS levels
The 74HCT107: TTL levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
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